Description: Formal Equivalence Checking and Design Debugging, Hardcover by Huang, Shi-Yu; Cheng, Kwang-Ting, ISBN 079238184X, ISBN-13 9780792381846, Like New Used, Free P&P in the UK Reviews the electronic design problems that require logic equivalence checking, describes the underlying technologies that are used to solve them, and presents in detail some novel approaches to verifying design revisions after re-timing or other intensive sequential transformations. Considers symbolic, incremental, and RTL-to-gate verification. Also surveys previous and recent literature on diagnosing and correcting design error, and analyzes the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by Huang and Cheng. Double spaced. Annotation c. by Book News, Inc., Portland, Or.
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Book Title: Formal Equivalence Checking and Design Debugging
Number of Pages: 229 Pages
Language: English
Publication Name: Formal Equivalence Checking and Design Debugging
Publisher: Springer
Publication Year: 1998
Subject: Computer Science, Physics
Item Height: 235 mm
Item Weight: 1170 g
Type: Textbook
Author: Kwang-Ting (Tim) Cheng, Shi-Yu Huang
Subject Area: Electrical Engineering
Series: Frontiers in Electronic Testing
Item Width: 155 mm
Format: Hardcover
