Formal Equivalence Checking and Design Debugging by Shi-Yu Huang (English) Hardc

Description: Formal Equivalence Checking and Design Debugging by Shi-Yu Huang, Kwang-Ting Cheng Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. FORMAT Hardcover LANGUAGE English CONDITION Brand New Publisher Description This text covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution.This book is intended for the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits. Table of Contents 1 Introduction.- 1.1 Problems of Interest.- 1.2 Organization.- I Equivalence Checking.- 2 Symbolic Verification.- 3 Incremental Verification for Combinational Circuits.- 4 Incremental Verification for Sequential Circuits.- 5 AQUILA: A Local BDD-based Equivalence Verifier.- 6 Algorithm for Verifying Retimed Circuits.- 7 RTL-to-Gate Verification 123.- II Logic Debugging.- 8 Introduction to Logic Debugging.- 9 ErrorTracer: Error Diagnosis by Fault Simulation.- 10 Extension to Sequential Error Diagnosis.- 11 Incremental Logic Rectification. Promotional Springer Book Archives Long Description Formal Equivalence Checking and Design Debugging covers two major topics in design verification: logic equivalence checking and design debugging. The first part of the book reviews the design problems that require logic equivalence checking and describes the underlying technologies that are used to solve them. Some novel approaches to the problems of verifying design revisions after intensive sequential transformations such as retiming are described in detail. The second part of the book gives a thorough survey of previous and recent literature on design error diagnosis and design error correction. This part also provides an in-depth analysis of the algorithms used in two logic debugging software programs, ErrorTracer and AutoFix, developed by the authors. From the Foreword: With the adoption of the static sign-off approach to verifying circuit implementations the application-specific integrated circuit (ASIC) industry will experience the first radical methodological revolution since the adoption of logic synthesis. Equivalence checking is one of the two critical elements of this methodological revolution. This book is timely for either the designer seeking to better understand the mechanics of equivalence checking or for the CAD researcher who wishes to investigate well-motivated research problems such as equivalence checking of retimed designs or error diagnosis in sequential circuits. Kurt Keutzer, University of California, Berkeley Details ISBN079238184X Author Kwang-Ting Cheng Short Title FORMAL EQUIVALENCE CHECKING & Series Frontiers in Electronic Testing Language English ISBN-10 079238184X ISBN-13 9780792381846 Media Book Format Hardcover Series Number 12 Year 1998 Place of Publication Dordrecht Publisher Springer Pages 229 Imprint Springer Country of Publication Netherlands Illustrations XVIII, 229 p. DOI 10.1007/b116726;10.1007/978-1-4615-5693-0 Edition Description 1998 ed. Edition 1998th Publication Date 1998-06-30 Alternative 9781461376064 DEWEY 005.14 Audience Undergraduate We've got this At The Nile, if you're looking for it, we've got it. With fast shipping, low prices, friendly service and well over a million items - you're bound to find what you want, at a price you'll love! TheNile_Item_ID:96221316;

Price: 378.29 AUD

Location: Melbourne

End Time: 2025-01-05T08:13:02.000Z

Shipping Cost: 18.32 AUD